1. Field of the Invention
This invention relates to logic circuits and more particularly a current mode logic circuit.
2. Description of the Prior Art
In the past, input current mode logic gates normally drive emitter-follower output transistors. By way of example, the basic logic circuits are illustrated in U.S. Pat. No. 3,259,761, Narud et al., assigned to the same assignee as the present invention. In this logic implementation, the collector terminal of the reference switching transistor of one input gate is normally collector-dotted or directly connected to a like collector terminal of other reference transistors associated with additional input gates forming the overall logic block. This node is then connected to a single emitter-follower output transistor. For optimum results, the emitter terminal of a clamping transistor also is connected to this node, as is well known in the prior art. The clamping transistor attempts to maintain the collector-dot node at constant voltage level regardless of the number of input gates being switched to a conductive state.
In this collector-dot application even with the use of a clamping transistor, the generated down level of the emitter-follower output transistor experiences voltage level shifts for each additional input gate that is rendered to a conductive state. Transient spikes are generated during level shifts. Accordingly, the noise tolerance level of the overall logic circuit is deleteriously affected.
Similarly, in other logic applications, the collector terminals of the reference switching transistors associated with a logic input gate are each individually connected to an associated emitter-follower output transistor, and then the emitter terminals of each of the output emitter-follower output transistors are emitter-dotted or directly connected.
In the emitter-dotted environment, the total output current from an emitter-dotted logic block is a relatively fixed value. Thus with only one emitter-follower of the logic block in the conductive mode, the total output current is essentially supplied through one emitter-follower. When a second or additional emitter-follower is rendered conductive while the first emitter-follower is also conductive, then less current is supplied or required to be supplied by the initially conducting emitter-follower, as the other conducting emitter-followers contribute their proportional amount. These current transients generate a negative spike associated with the up level signal. Again, this reduces the noise tolerance levels of the overall logic block.
Moreover, the use of a clamping transistor in the collector-dot case causes additional temperature compensation problems as the emitter terminal of the emitter-follower output transistor resides at two base-to-emitter voltage drops, i.e., the base-to-emitter drop of a clamp transistor and that of the emitter-follower output transistor. Since temperature compensation tolerances are related to the number of individual base-to-emitter voltage drops, it can be seen that the additional base-to-emitter voltage drop of the clamping transistor renders the overall generated output voltage more susceptible to temperature changes.